Disk apparatus used with a recording medium having clock marks detected by clock interpolation

ABSTRACT

Clock marks for sampling clock components have been formed in advance at constant intervals along the tracks of a disk recording medium and, when rotationally driving the disk recording medium, these clock marks are detected to sample clock components. By sampling the clock component from the clock marks thus formed at fixed periods and further generating an interpolation clock in a region between the clock marks on the basis of the sampled clock component, a very accurate clock can be obtained, as compared to the case in which a clock is sampled from reproducing code. Consequently, there can be realized a further large-capacity disk recording medium.

TECHNICAL FIELD

The present invention relates to a disk apparatus, and is applicable to,for example, a hard-disk apparatus.

BACKGROUND ART

In the hard disk, each of a plurality of data recording areas(hereinafter referred to as tracks) concentrically arranged with respectto the center of the disk is divided into a plurality of blocks(hereinafter referred to as sectors), and data are divided and recordedon these sectors. In hard-disk apparatuses, there has been adopted asector servo method as a servo method which is used in reading data fromsectors.

This servo method asynchronously detects a servo header from eachsector, locks phase-locked loop (PLL) output by means of a synchronous(SYNC) pattern and the like, and generates various types of timingsignals based on the PLL output.

A gap region (redundancy signal region, etc.) of a specified length wastherefore needed in front of a servo zone, as shown in FIG. 1.

However, this servo method, as shown in FIG. 2, has the problem that,while the position and the time near the head of the sector can becontrolled relatively accurately, accurate control near the end (pointsP1 and P2 of the figure) of the sector becomes more difficult.

That is, since the sector servo method generates a synchronizing signalat a unit of several tens of sectors per one lap of the track, it cannotfollow a change in the time axis such as a change in the rotation of thedisk and cannot obtain the positions of as many as several ten thousandsof bit units per one lap with a high degree of accuracy.

The number of regions to which servo information is given can beincreased to solve this, but it is hard to improve the track densityfrom the viewpoint of accuracy of writing because the sector servomethod writes the servo information in units of sectors. Likewise, theposition on the disk could not be fixed with a high degree of accuracyfor this reason.

SUMMARY OF THE INVENTION

Considering the above points, the present invention provides a diskapparatus in which an angular position on the track can be specifiedwith a high degree of accuracy without increasing the area occupied byservo information.

To solve such problems, the present invention includes a rotationaldrive means for rotating and driving a disk recording medium (2) havinga plurality of clock marks (CM) formed in advance at constant intervalsalong recording tracks, a recording and/or reproducing means (3) forrecording and/or reproducing desired data on/from the disk recordingmedium (2), and a clock interpolation means (5B, 5C) for detecting theplurality of clock marks (CM) appearing at definite periods from areproducing signal (S2) reproduced by the recording and/or reproducingmeans (3), and for generating an interpolation clock (PLL clock)subdividing a time axis between the plurality of clock marks (CM) basedon a clock component sampled from the plurality of clock marks (CM).

The clock component is sampled from a plurality of clock marks CM formedin advance at constant intervals along the tracks of the disk recordingmedium, and an interpolation clock (PLL clock) subdividing between clockmarks (CM) is generated. Thus, the clock component is sampled based noton self-clock contained in reproducing code but on the physically formedclock marks (CM) having a definite period. By generating theinterpolation clock (PLL clock) based on this, a very accurateinterpolation clock (PLL clock) can be obtained. As a result, theabsolute coordinate position on the disk recording medium 2 can also befixed precisely.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic diagram showing a conventional sector structure;

FIG. 2 is a schematic diagram explaining an asynchronous sector servomethod;

FIGS. 3(A) to 3(D) are schematic diagrams showing a data structure thatis formed on a disk recording medium of the present invention;

FIGS. 4(A) to 4(C) are schematic diagrams explaining a hierarchical datastructure in the servo pattern zone;

FIG. 5 is a schematic diagram explaining the array of segmentsconstituting a sector;

FIG. 6 is a table showing the dimensions of elements forming a clockmark;

FIG. 7 is a schematic diagram explaining a method of magnetizing adisk-shaped recording medium;

FIG. 8 is a block diagram showing an embodiment of a disk apparatus;

FIG. 9 is a block diagram showing the constitution of the predictivegate generating circuit;

FIG. 10 has timing charts (A) to (G) explaining detection timings of thePLL output, the clock mark, the frame synchronizing mark, and the homeindex mark;

FIG. 11 is a block diagram showing the constitution of the PLL circuit;and

FIG. 12 is a table explaining the operation sequence of the PLL circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of the present invention will be described with referenceto the accompanying drawings:

(1) Disk Recording Medium

It is assumed that a large number of clock marks has been formed inadvance on a magnetic disk used in this embodiment, and this embodimentis made to constitute a very accurate synchronizing system by lockingthe PLL clock of a PLL circuit to the clock marks appearing at fixedperiods after driving the disk. This servo method will hereinafter bereferred to as a sampled servo method. This magnetic disk will also bereferred to as a preembossed rigid magnetic (PERM) disk.

Incidentally, since the clock marks are spaced and not provided in thedata areas, the clock components in the regions are generated by the PLLcircuit that is operated in synchronization with the clock marks. Atthis time, unlike the case where a clock is generated from clockpatterns asynchronously provided or the case where a clock is generatedfrom a self-clock code array, the PLL clock that is output from the PLLcircuit is obtained with a high degree of accuracy because it isgenerated based on a periodic clock permanent formed. Thus, arbitraryposition coordinates on the disk can be determined accurately bysynchronizing the PLL clock with the phase of the clock marks preciselyformed in advance on the tracks of the magnetic disk.

(1-1) Format

Incidentally, even if the PLL clock corresponded to the magnetic disk,the absolute coordinates on the magnetic disk could not be fixed by onlythat PLL clock. To determine the absolute coordinates, it is necessaryto fix a reference position appearing once for one rotation.

For this reason, special marks hardly appearing in data and clock marksare physically formed or written as home index marks on the magneticdisk.

In addition, frame synchronizing marks whose appearance frequency ishigher than that of the home index marks are provided so that the PLLclock can be recovered to its locked state for a short period of timewhen the locked state of the PLL clock is released.

This structure will hereinafter be described on the data structure ofthe magnetic disk.

(1-1-1) Physical Disk Structure

A physical data structure that is provided in advance on the magneticdisk will first be described using FIG. 3.

The magnetic disk uses a three-hierarchy structure consisting of aplurality of tracks (FIG. 3(A)) arranged concentrically with respect tothe center of the magnetic disk, a plurality of sectors (FIG. 3(B))constituting the track, and a plurality of subblocks (FIG. 3(C))constituting the sector. The subblocks will hereinafter be referred toas segments.

Among these, the segment is the minimum unit on the servo format. Onesegment consists of a servo pattern zone (address pattern, clock mark,and fine pattern) and a data zone (FIGS. 3(D)). The length of eachsegment is equal to two hundred PLL clocks (each of which is a minimumclock that is generated from a clock mark and each of which is given ata data bit rate). One sector consists of 14 segments, and one trackconsists of 60 sectors. Therefore, one track (one rotation) consists of840 (=14×60) segments.

Thus, the lattice point of the angular coordinates on the magnetic diskcan be given by detecting the clock marks respectively recorded on the840 segments. That is, a virtual rotary encoder is constituted bysynchronizing the PLL clock with the clock mark. Note that, the sectorand segment used in this embodiment are a format of marks physicallyformed, and are not always identical with logic sectors used when datais written.

It is also assumed in this embodiment that, as with the clock marks, allof the address patterns and the fine patterns constituting the servopattern zone have also been formed at the time of manufacturing.

(1-1-2) Structure of Servo Pattern Zone

The absolute coordinates of the magnetic disk formed in a physicalformat such as this can be specified by the servo patterns provided onthe magnetic disk as follows:

Each of 60 sectors appearing on one track (one lap) is made so that thestarting position thereof can be detected by a special pattern of theservo pattern zone recorded on the head segment of each sector.

For this special pattern there is a home index mark appearing once forone rotation and a frame synchronizing mark appearing 59 times for onerotation.

The head segment of the sector in which the home index mark is providedwill first be described. This segment is called a home index segment andhas the data structure shown in FIG. 4(A). The concrete pattern exampleof the data structure is shown in FIG. 3(D1). To an address pattern ofthis home index segment are written a home index mark and an addressmark. A reference position and a track number on the track can beidentified by these marks.

On the other hand, the head segment of the sector in which the framesynchronizing mark is provided is called a frame synchronizing segmentand has a data structure shown in FIG. 4(B). The concrete patternexample of the data structure is shown in FIG. 3(D2). On this framesynchronizing segment, a frame synchronizing mark and an address markare written as an address pattern. A starting position and a tracknumber of each sector can be identified by these marks.

Each of the home index segment and frame synchronous segment is called aheader segment.

The other segments are called plain segments and discriminated from theheader segment. These plain segments are 13 segments following the homeindex segment and 13 segments following each frame synchronizingsegment. That is, each sector comprises a single header segment and 13plain segments.

The data structure of each plain segment is shown in FIG. 4(C). Theconcrete pattern example is shown in FIG. 3(D3). An address code iswritten as an address pattern on this plain segment so that the tracknumber can be identified.

If part of a single track on the magnetic disk in which the physicalsegments have been formed is expressed with this relationship, it willbecome as shown in FIG. 4.

Hence, only clock mark CM of the patterns constituting the servo patternzone is used to synchronize the PLL clock, and the address pattern isused to specify the coordinates. Also, only when the address pattern andthe fine pattern are applied to the magnetic disk apparatus, there aresome cases in which they are used for other purposes.

(1-1-2-1) Functions of Individual Marks

As described in the foregoing paragraph, the servo pattern zone isconstituted of a combination of a plurality of patterns. In thisparagraph, the functions of each pattern including the already describedpatterns will be described in detail.

First, the home index mark is a signal for determining the referenceposition of the track. That is, this mark fixes a 0-th sector among 60sectors on each track and indicates the start (R-θ coordinate origin) ofthe track. R represents a radius direction, and θ represents angularcoordinates. This home index mark is not provided in the plain segments.

On the other hand, the frame synchronizing mark is a signalrepresentative of the starting position of each sector. The markrepresents the head segment of each of first, second, . . . , and 59thsectors. When the PLL clock is locked as the magnetic disk is driven,the frame synchronizing mark also functions as a mark for finding theclock mark. The home index mark also does the same function. The framesynchronizing mark is not provided in the plain segments.

The address mark, which constitutes the address pattern together withthese two types of marks, is a mark for obtaining rough addressinformation (track number) and is provided in all of the segments. An18-bit Gray code is used to represent this data.

Clock mark CM is also a mark for notifying the circuit system ofcoordinate information together with the rotational phase of themagnetic disk. A single clock mark is provided in each segment. In amagnetic disk made on an experimental basis, the length of one PLL clockis assigned to clock mark CM.

Further, the fine pattern is a signal for obtaining information on aposition being within one track and comprises four marks X, Y, A, and B(FIGS. 3(D1) to 3(D3)). The fine pattern is provided in all of thesegments. These patterns are formed as one island for one PLL clock. Thelength in the radial direction is equal to the track pitch and the arrayis a four-phase zigzag pattern used in the sector servo method.

(1-1-3) Trial Example

The magnetic disk was made on an experimental basis by forming thenecessary concavities and convexities on a glass substrate by etching,and then depositing a magnetic film over the whole of the disk bysputtering. Hence, each mark section is formed into a concave shape, andthe section other than the mark section (corresponding to a "sea") isformed into a convex shape. The dimensions of the formed disk are shownin FIG. 6. In the trial example, the minimum mark length on theinnermost circumference (radius 15.5 mm!) of the disk is 0.6 μm! and theminimum mark length on the outermost circumference (31 mm!) is 1.2 μm!.

After the concave and convex portions have thus been formed, themagnetic disk was made by DC-magnetizing it using a magnetic head sothat the magnetized directions of the concave and convex portions becomeopposite. The mark output signal is detected by the magnetic head. Amethod of magnetizing the concave and convex sections is shown in FIG.7. The concrete magnetization method is described in Japanese PatentApplication No. 217935/1992 by the present applicant.

The frame synchronizing mark, the home index mark, and the clock markCM, which are also formed with these concavities and convexities, arearranged so that, even if the magnetic disk apparatus were in a seekoperation, these marks could be detected to hold the locked state of thePLL circuit. That is, these marks are a continuous pattern on thetraveling locus (locus of rotational movement) of the magnetic head sothat, even if the magnetic head was in any position on the magneticdisk, they could be detected.

Therefore, the frequency of the clock marks that are reproduced from themagnetic disk described in this embodiment becomes 50.4 ks/sec! when thenumber of rotations of the disk is 3600 rpm! (i.e., 60 Hz!). Also, sincea signal that is synchronized to this clock signal is a signal that is200 times the frequency of the PLL clock, the oscillating frequency ofthe PLL clock becomes 10.08 MHz!.

(1-2) Advantages of the Embodiment

According to the constitution described above, all of the segments arerecorded not by the same patterns but by hierarchical servo patternsappearing at a hierarchical appearance probability, so that the rate ofthe servo area occupying one track length can be relatively reduced ascompared to the case where the same patterns are recorded for all of thesegments. For example, the frame synchronizing pattern is one-fourteenththe appearance probability of the clock mark. Therefore, if the servopattern is formed by this method, the occupied rate of the servo patternlength to one track length can be reduced to about 10%. Thus, theoccupied area can be compressed as compared to the case of thesynchronizing pattern being used for each segment. Further, in themagnetic disk, the bit length of the embossed system becomes severaltimes a data recording bit waveform, as compared to a magneticallyrecorded bit wavelength, and therefore this effect is large.

In addition, since the clock components reproduced from this magneticdisk are obtained from the clock marks that have physically beenprovided in advance, the rotational information of the magnetic disk canbe obtained with fidelity, and a virtual rotary encoder of a completesynchronizing system can be formed easily.

(2) Magnetic Disk Unit

(2-1) Constitution of Magnetic Disk Unit

In FIG. 8, 1 denotes a magnetic disk apparatus. It is assumed that allof the clock marks have been formed in advance on a magnetic disk 2 thatis reproduced by the magnetic disk apparatus 1, and data has beenrecorded by partial response (PR) code. The magnetic disk apparatus 1reads from a magnetic head 3 a reproducing signal S1 corresponding to amagnetization pattern recorded on the magnetic disk 2 and sends it to aread/write amplifier 4. Hence, in this embodiment, the magnetic head 3comprises a magneto resistive (MR) inductive composite thin-filmmagnetic head.

The read/write amplifier 4 amplifies the reproducing signal S1 and givesit to a sampled servo system 5, tracking servo system 6, and a signalprocessing system 7.

Here, the tracking servo system 6 detects a relative positionalrelationship in the radius direction between the magnetic head 3 and thetrack by means of a track position detection circuit 6A, and controls adrive part 6B so that the magnetic head 3 can run on the trackaccurately.

The signal processing system 7 also decodes recorded data by means of awaveform equalizer/decoder 7A from the reproducing signal S1 reproducedfrom the data area, and the decoded data is signal processed by means ofdata processing part 7B. Hence, in the decoding operation in thewaveform equalizer/decoder 7A there is employed a maximum likelihoodsequence estimation.

(2-1-1) Constitution of Sampled Servo System

The constitution of the sampled servo system 5 will next be describedusing FIGS. 8 to 11.

The sampled servo system 5 is constituted of a binary detection circuit5A for converting the reproducing signal S1 into a binary signal S2, atiming gate circuit 5B for sampling a clock component from the binarysignal S2, and a PLL circuit 5C that operates, as a reference signal,the clock component that is given by the timing gate circuit 5B.

(2-1-1-1) Constitution of Timing Gate Circuit

The timing gate circuit 5B is made to operate, as a reference clock, aPLL clock that is output from a PLL circuit 5C, and made to predict thetiming at which the clock mark, the frame synchronizing mark, and thehome index mark appear, based on the PLL clock, and generate a timinggate signal.

This circuit part is a predictive gate generation circuit section 5B1.

As shown in FIG. 9, the predictive gate generation circuit section 5B1is constituted of three gate stages of a timing gate stage (binarycounter 5B11 and decoder 5B12) for predicting the appearance of a clockmark and generating a timing gate signal, a timing gate stage (binarycounter 5B13 and decoder 5B14) for predicting the appearance of a framesynchronizing mark and generating a timing gate, and a timing gate stage(binary counter 5B15 and decoder 5B16) for predicting the appearance ofa home index mark and generating a timing gate.

First, the predictive gate generation circuit 5B1 inputs a PLL clockshown in FIG. 10(G) to the binary counter 5B11 constituting the timinggate stage for a clock mark and counts the number of clocks. The decoder5B12 outputs timing gate signal S5 each time the counter value of thebinary counter 5B11 reaches 200. Thereby, a timing gate signal S5 thatis 200 times the frequency of the PLL clock is obtained as shown in FIG.10(F).

Clock mark detection circuit 5B2, when reproducing signal S1corresponding to the clock mark is input during the time timing gatesignal S5 is rising, outputs this as a gated clock signal (FIG. 10(E)).Of course, there are a few clock marks CM that are found during the timethe PLL clock is not synchronized with the clock mark CM.

Employing timing gate signal S5 in this way is for preventing a falseclock component included in the reproducing signal S1 from beingdetected as a clock signal CM by mistake, and for sampling only a clockcomponent corresponding to a true clock mark.

Further, the gate width of the timing gate signal S5 has been set to beslightly wider than the pulse width of the reproducing signal S1obtained from the clock mark CM. Thereby, when a clock componentcorresponding to the clock mark CM becomes near to the phase of the PLLclock, it is made to be pulled quickly into a locked state.

Incidentally, after starting, it is difficult to lock the phases of allof the clocks abruptly to obtain the absolute coordinates. The magneticdisk apparatus 1 therefore operates so that the frame phase is firstlocked on the frame synchronizing mark and the home index mark whichappear at the same rate as the period of rotation of the spindle motorand at the frequency of one-fourteenth of clock mark CM. For thisreason, the predictive gate generation circuit 5B1 predicts theappearance of the mark (i.e., frame synchronizing mark and home indexmark) of the head segment of the sector and generates timing gate signalS6 (FIG. 10(D)). The magnetic disk apparatus 1 shifts from within theperiod given by the timing gate signal S6 to an operation of detectingthe frame synchronizing mark.

The timing gate signal S5 predicting the clock mark is first input tothe binary counter 5B13 to count the number of clocks. Next, timing gatesignal S6 predicting the timing at which the frame synchronizing markthat is 14 times the counted value will be detected, is generated. Thetiming gate signal S6 is applied from the decoder 5B14 to a frame markdetection circuit 5B3. The frame mark detection circuit 5B3 counts thenumber of the frame synchronizing marks or the home index marks withinthe period given by the timing gate signal S6, determines the framephase to be locked if 60 marks are found per one rotation and outputsthe frame mark signal, and resets the frame value of the counter of adisk-surface absolute-position detection counter.

If the frame phase is locked by these operations, all of the gatedclocks will be detected. Then, timing gate signal S7 (FIG. 10(B))predicting the appearance of the home index mark is generated at apredictive gate generation circuit 5B1 to detect the home index segmentappearing at a frequency of 1/60 with respect to the sector.

At this time, a binary counter 5B15 inputs therein the timing gatesignal S6 predicting the frame synchronizing mark, to count the numberof clocks. A decoder 5B16 sends a signal that is 60 times this countedvalue to a home index mark detection circuit 5B4 as timing gate signalS7 predicting the home index mark. If the home index mark is detected atthis timing (FIG. 10(A)), the home index mark detection circuit 5B4outputs the home index signal and resets the master reset terminal ofthe disk-surface absolute-position detection counter. Thereby, anaddress completely synchronized with the rotating magnetic disk isgenerated at the disk-surface absolute-position detection counter.

(2-1-1-2) Constitution of PLL Circuit

Hence, a PLL circuit 5C constituting the sampled servo system isconstituted as shown in FIG. 11. The PLL circuit 5C inputs gated clocksignal S_(CK) output from the clock mark detection circuit 5B2 to phasecomparator 5C1, to compare its phase with the phase of the output ofdivider 5C2. A loop filter 5C3 applies a DC voltage proportional to thedifference in phase between the two signals to a voltage-controlledoscillator (VCO) 5C4 so that the PLL clock is locked on gated clockS_(CK).

(2-2) PLL Operation

In the above-described constitution, the reproducing operation of themagnetic disk apparatus 1 will be described on the servo operation ofthe sampled servo system 5.

If the loop constant of a loop filter 5C3 constituting the PLL circuit5C is designed to be a suitable value, the spindle motor will start andalso the PLL circuit 5C will start following. After the rotation of thespindle motor has reached a steady rotation (60 Hz!), it is expectedthat the oscillating frequency of the PLL circuit 5C will reach a steadystate.

However, in the case of this embodiment, the PLL clock is locked on theclock mark on the magnetic disk further reliably and quickly byoperating the PLL circuit 5C in the following sequences:

These series of sequences by the magnetic disk apparatus 1 will bedescribed using FIG. 12.

The operating condition of the PLL circuit 5C immediately after startingis not fixed, and a phase comparator 5C1 and a voltage-controlledoscillator 5C4 are both operating unstably. That is, the phasecomparator 5C1 outputs random errors and the voltage-controlledoscillator 5C4 runs freely. At this time, in the timing gate circuit 5B,only clock mark detection circuit 5B2 is operating based on the PLLclock.

At this time, reproducing signal S1 sampled by timing gate signal S5 isto be output by the clock mark detection circuit 5B2 to the PLL circuit5C, but, at this point in time, in most cases, gated clock SCK does notcontain the clock component corresponding to the clock mark CM.

Further, the counter value of the counter applying the absolute positionon the disk is also unfixed.

If the number of rotations of the spindle motor soon comes near thesteady rotational frequency (60 Hz!), some of gates clock signals S_(CK)obtained from the clock mark CM immediately after the framesynchronizing mark and the outputs of the voltage-controlled oscillator5C4 of the PLL circuit 5C will reach a normal phase relation, and thephase comparator 5C1 will normally operate only immediately after theframe synchronizing mark FM.

Therefore, the oscillating frequency of the voltage-controlledoscillator 5C4 becomes pulled into the normal phase at a frequency ofabout 60 times per rotation (frame synchronizing mark detectionprocess), and the oscillating frequency of the voltage-controlledoscillator 5C4 begins to approach the normal phase. After the end ofthis process, the oscillating frequency of the voltage-controlledoscillator 5C4 reaches (process of detecting all clocks) a normalfrequency (10.08 MHz!).

When the oscillating frequency of the PLL circuit 5C4 reaches the normalfrequency in this way, the total number of gated clocks S_(CK) (840clocks) will be detected correctly from the track being scanned and boththe phase comparator 5C1 and the voltage-controlled oscillator 5C4 willbe controlled at a frequency of 50.4 KHz!.

As the control points are thus increased, the phase relation of the PLLclocks that are output from the voltage-controlled oscillator 5C4 isheld in a close relationship to the clock phase of the magnetic disk.However, in the stage, only the PLL clock is locked and the state (orframe phase) of the address decoder counter is unfixed.

If it is detected that the phase relationship has become a closerelationship, the frame synchronizing mark signal is applied to thereset terminal of the disk-surface absolute-position detection counterand the counter enters a frequency state in which it rotates 60 timesper lap of the magnetic disk. The frame phase is fixed for this reason.That is, the state arises in which the clocks of all of the segmentswere found.

However the origin position of the track arranged on the magnetic diskstill remains unfixed.

Then, if frame synchronization is identified from the number of clocksthat is output from the frame mark detection circuit 5B3 to which thetiming gate signal predicting the frame synchronizing mark FM isinputted, the timing gate predicting the home index mark is opened, andcomplete synchronization is detected by applying the home index signalpassed through this predictive timing gate to the master reset terminal,and the PLL clock is shifted to the steady state. That is, the PLL clockthat has been phase-locked in bit order is obtained.

In addition, there are some cases in which the synchronization state isseldom lost by the seek operation and the like, but in a case wherethere is a means for detecting that synchronization is lost, the PLLclock can automatically be pulled into resynchronization state byreturning to any one of the above-described series of sequences(starting, clock detection immediately after frame mark, clock detectionof all segments, and home index detection) in accordance with the statein which synchronization was lost.

As a result, there is obtained a precise servo clock following thesubstrate coordinate system of the magnetic disk accurately.Incidentally, after reaching the locked state, this clock is used in thetiming control of the servo system and the signal processing systemwithin the magnetic disk apparatus. Once locked, there will nopossibility that the locked state would be lost even if several of theclock marks were lost, and the servo clock can keep generating accuratetiming.

However, since the magnetic disk that is formed is attached to thespindle motor, there exists eccentricity and therefore there are casesin which the time interval of the clock marks reproduced from themagnetic disk changes according to the radial vibrations. If this changeremains as is, the phase shift with the servo lock become a residualdifference. For this reason, a quantity of eccentricity measured inadvance is applied to the PLL circuit 5C to absorb the phase shift.

If the PLL clock enters the locked state, the integration timing, thesample hold timing, and the address decode timing will be outputaccurately to the position signal generation section. The servooperation is performed by using the position signal obtained in thisway.

(2-3) Advantages of the Embodiment

According to the above-described arrangement, a series of sequences forsynchronizing the PLL clock of the PLL circuit to the clock mark of themagnetic disk is divided into hierarchical multiple stages, so the phasecan be pulled quickly into the locked state, as compared to the priorart.

Particularly, when high-speed access to a plurality of magnetic disks isfrequently required like a hard disk, shortening the time for a shift tothis synchronization state is noticeably effective.

Also, since a shift state to the locked state can be performed inmultiple stages, a return operation to the locked state would not needto be repeated from the initial state even if the locked state were lostand therefore a shift to the locked state can be shortened.

Further, there also occurs the advantage that the self-locking of thesignal processing system can be made unnecessary. This is not alwaysnecessary in a servo system, but it is effective particularly in amethod combining partial response coding and maximum likelihooddecoding, such as a conventional signal processing method in whichself-locking is hard to sample, compared to a combination method of 1-7or modulation and peak detection.

(3) Other Embodiments

The above-described embodiment has been set forth with relation to amagnetic disk and a magnetic disk apparatus. However, the presentinvention is not only limited to this, but may be applied to opticaldisks and optical disk apparatues. The same effect as theabove-described embodiment can also be obtained. In addition, theinvention is also applicable to optical magnetic disks and opticalmagnetic disk apparatuses and the same effect as the above-describedembodiment can be obtained.

Further, in the above-described embodiments, the magnetic head comprisesan MR head, but it may also be applied to other high-density heads. Inaddition, it may also be applied to the case of an optical pickup.

Further, in the above-described embodiments, the clock marks have beenformed in advance as embossed marks, but they do not always need to berecorded as embossed marks, and the present invention is not onlylimited to this, but they may also, be recorded magnetically.

Further, in the above-described embodiments, one track comprises 60sectors, one sector comprises 14 segments, and one segment is a200-clock length: However, the present invention is not only limited tothis, but these may also take other numerical values.

Further, in the above described embodiments, the physical structure ofone track is a three-level structure (track: sector, segment). However,the present invention is not only limited to this, but it may also beapplied to a four- or more-level structure. Likewise, while there hasbeen described the case in which the structure of the servo pattern is athree-level structure (home index mark+address mark, frame synchronizingmark+address mark, address mark), the servo pattern may also be appliedto a four- or more-level structure.

Industrial Applicability

The present invention is applicable particularly to a disk apparatusthat reads and/or reproduces data from disk recording medium:

We claim:
 1. A disk apparatus for recording and/or reproducing desireddata on/from a disk recording medium, comprising:rotational drive meansfor rotationally driving said disk recording medium which comprises aplurality of recording tracks, each of which comprises a plurality ofsectors, each of which comprises a plurality of segments, each of whichhaving a clock mark, resulting in a plurality of clock marks formed inadvance at constant intervals along said recording tracks wherein eachof said plurality of sectors comprises a single header segment and aplurality of plain segments wherein a home mark is disposed on one ofthe header segments of respective sectors on the recording track and aframe mark is disposed on other header segments of said plurality ofsectors; recording and/or reproducing means for recording and/orreproducing desired data to/from said disk recording medium; and clockinterpolation means for detecting the plurality of clock marks appearingat fixed periods from a reproducing signal reproduced by said recordingand/or reproducing means, and for generating an interpolation clocksubdividing a time axis between said plurality of clock marks based on aclock component sampled from the plurality of clock marks, wherein saidclock interpolation means includes means for detecting the clock mark,means for detecting the frame mark in accordance with the detected clockmark and means for predicting the home mark from the detected frame markand the detected clock mark to synchronize in rotation said rotationaldrive means; wherein said clock interpolation means comprises: a PLLcircuit for outputting a PLL output used as said interpolation clock; acounter for counting the number of clocks of said PLL output, and adecoder for generating a gate signal for sampling said clock componentfrom said disk recording medium by decoding the counted value.
 2. Thedisk apparatus according to claim 1, wherein said disk recording mediumis a magnetic disk.
 3. The disk apparatus according to claim 2, whereinsaid plurality of clock marks is magnetically recorded.
 4. The diskapparatus according to claim 1, wherein said plurality of clock marks isan embossed type.
 5. The disk apparatus according to claim 4, whereinsaid clock interpolation means feedforward-compensates for saidinterpolation clock according to the quantity of eccentricity of thedisk measured in advance.